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| dev:drumgizmo_in_a_box [2017/06/20 20:04] – suhr | dev:drumgizmo_in_a_box [2017/10/03 21:34] (current) – deva | ||
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| ====== Drumgizmo in a box ====== | ====== Drumgizmo in a box ====== | ||
| + | * [[dev: | ||
| * [[http:// | * [[http:// | ||
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| * http:// | * http:// | ||
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| - | * https:// | + | * [[https:// |
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| multiplexer 16bit pr. channel to 2 bit per channel (ie. 2 channels per 32 bit sample) and write 20 channels in total this way where the 16 is the actual output and the last 4 are unused (but can be used for sync) | multiplexer 16bit pr. channel to 2 bit per channel (ie. 2 channels per 32 bit sample) and write 20 channels in total this way where the 16 is the actual output and the last 4 are unused (but can be used for sync) | ||
| + | |||
| + | ^^ Just set least signifiant bit to zero on all channels except last channel | ||
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| Bring logic analyzer and rpi3 and probes | Bring logic analyzer and rpi3 and probes | ||
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| + | ===Synchronisation between SPI/ALSA and FPGA=== | ||
| + | Each sample uses 1 bit as sync bit. | ||
| + | Channel 0 has the bit set to 1, the rest has it set to 0. | ||
| + | If the FPGA detects a drift, (pattern doesn' | ||
| + | While seeking for a new lock pattern, the output should be muted. When the lock pattern has been found again a number of samples should be processed before the output is unmuted again in order to make sure that we didn't simply find an audio pattern that matched the lock pattern (highly unlikely!) | ||
| + | |||
| + | CS on the SPI can be used as a reset mechanism, ie. CS high will reset the FPGA channel counter. | ||
| + | CS could be set high for each 1024 samples or similar, key-frame style. | ||
| ===Future ideas=== | ===Future ideas=== | ||
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| ===Tasks=== | ===Tasks=== | ||
| * DG (+ dependencies) Yocto recipe | * DG (+ dependencies) Yocto recipe | ||
| - | * Codecs breakoutboard | + | * Design print |
| + | * Add PCM3168A as kicad component {{: | ||
| * ALSA SPI driver | * ALSA SPI driver | ||
| * Codec configuration (Read datasheet) | * Codec configuration (Read datasheet) | ||
| * Data transfer | * Data transfer | ||
| * FPGA / Shift array (SPI to I2S) | * FPGA / Shift array (SPI to I2S) | ||